Binary counters are used in frequency-to-digital conversion to effect binary quantization of a variable-frequency signal. This is done in order to provide the frequency data in a form which is suitable for digital system processing. An exemplary application is illustrated in FIG. 1 of the accompanying drawings.
A sensor 10 forms part of an oscillator 12 which produces a square-wave output 14 indicative of the physical attribute (e.g. pressure) which the sensor is designed to measure. This output 14 is communicated to a prescaler 16 which produces as its output 18 a programmable, integral number of periods of the oscillator output 14. The prescaler output 18 is communicated to a control circuit 20. The control circuit 20, upon receiving a first command signal 22 from a microprocessor 24, generates a signal 26 which clears a binary counter 28. The signal 26 is again communicated to the counter 28 at its opposite state or logic level. This is followed by a gate enable signal 30, thus initiating a counting cycle which results in frequency-to-digital conversion. The control circuit 20, responding to the prescaler output 18, provides the gate enable signal 30 at a pulse width which is proportional to the oscillator output 14. The binary counter 28 receives a clock signal 32 communicated from a digital high-speed oscillator 34 as a wavetrain. The counter 28 successively divides the frequency of the clock signal 32 and generates an output 36. While enabled, the output 36 of the counter 28 is a plurality, "n", of wavetrains, each representing the bit state (i.e. 0 or 1) of a different whole-number order or power of the number two. To effect such representation, each wavetrain of successively higher order has a frequency which is half that of the wavetrain associated with the immediately lower order. Thus, if the zero-order wavetrain has a frequency of "f", then the first-order wavetrain has a frequency of "f/2", and so on, with the nth-order wavetrain having a frequency of "f/(n+1)". After the control circuit 20 ends the counting cycle via communication of a gate disable signal 30 to the counter 28, it sends a signal 38 to an interrupt input of the microprocessor 24. The bit states of the wavetrains at the end of the counting cycle are then read by the microprocessor 24 as a binary number representing a frequency datum.
An exemplary four-bit conventional binary counter 28 is illustrated in FIG. 2. The above-described frequency division is typically accomplished by a series 40 of D-type flip-flops. Each flip-flop receives a wavetrain at its clock input (as at 42) and provides at its true output (as at 44) a wavetrain having half the frequency of the input. The complement output (as at 46) of the flip-flop is an inverted wavetrain otherwise identical to the true output 44, and is communicated to the clock input of the next succeeding flip-flop. The original clock wavetrain ("REFCLOCK") is provided by an oscillator 32 (FIG. 1) and communicated to the clock input of the first-stage flip-flop 48. The output Q0 of the first-stage flip-flop 48 is the zero-order wavetrain, this having a frequency which is half that of REFCLOCK. The outputs Q1, Q2, Q3 of the second, third, and fourth flip-flops are the first-order, second-order, and third-order wavetrains, respectfully. The counting cycle is initiated and terminated by the gate signal ("GATE"), which is communicated through an AND-OR gate 50 to the "D" input 52 of the first-stage flip-flop 48. The counter 28 is cleared by a clear signal ("CLEAR") received between successive counting cycles. The timing associated with the data inputs GATE, REFCLOCK, CLEAR and data outputs Q0 . . . Q3 is illustrated in FIG. 3.
The resolution with which a binary counter can quantize frequency data is fundamentally limited by the frequency of the original clock wavetrain, REFCLOCK. Conventional binary counters further narrow this fundamental limitation by dividing that frequency before producing the zero-order wavetrain, Q0.
The primary objective of this invention is to double the resolution with which binary counter circuits quantize frequency data.
A further objective of the invention is to provide both synchronous and ripple binary counter circuits which achieve the primary objective.